1. Technical Field
The present invention relates to integrated circuits intended for operating at very high frequency and more specifically to such circuits, some portions of which are sensitive to noise signals.
2. Description of the Related Art
For example, in the field of telecommunications and of portable phones, it is desired to integrate on a same chip logic signal processing circuits and analog amplifying circuits, intended for operating at very high frequencies, greater than 1 GHz, ranging for example from 2 to 10 GHz. In particular, a low-noise analog amplifier directly connected to the antenna output is generally provided. It is important to avoid that the noise resulting from the switchings of the digital signals affects the amplifier inputs since this noise would then be injected back into the circuit with a very high gain.
To test the sensitivity to noise of an integrated circuit and of various protection circuits, a test structure such as that shown in FIG. 1 may be used. In this test structure, the chip is divided into squares. For example, a chip portion having a 5-millimeter side is divided into 15×15 squares. A circuit likely to transmit square signals is formed in the first square (square C1-1 of the first column and of the first row) and the high-frequency signal collected in the other squares is studied. A portion of the component including the squares most diagonally distant from square C1-1 is surrounded with a protection structure 10. The quality of this protective structure is tested by comparing the noise collected in square C14-14 (fourteenth column, fourteenth row) arranged inside of the protective structure and the noise collected for example in square C1-15 (first column, fifteenth row) located substantially at the same distance from square C1-1 as the squares located inside of protective structure 10.
As illustrated by the partial cross-section view of FIG. 2, the case where the structure is formed on a lightly-doped P-type solid single-crystal silicon substrate 11 (P−) will more specifically be considered. The various components of the integrated circuit are assumed to be formed in an upper portion of this substrate, for example, in a lightly-doped N-type epitaxial layer, a portion 12 of which is shown at the limit of protective structure 10. The various components are for example directly formed in this epitaxial layer (case of the some bipolar transistors) or in more heavily-doped P-type wells (13) or N-type wells (14) in which N-channel and P-channel MOS transistors will in particular be found. The protective structure is formed of a heavily-doped P-type wall 15 connected to ground.
Such a protective structure is efficient at frequencies smaller than 1 GHz. However, as illustrated in FIG. 3, the protection is no longer efficient when the frequencies increase. This is in particular due to the fact that the connection between heavily-doped wall 15 and the ground inevitably includes an inductance 1 having an impedance which increases along with frequency.
FIG. 3 shows the attenuation in dB at the level of square C1-15 and at the level of square C14-14 of a signal transmitted by square C1-1, according to frequency (in logarithmic scale), between 100 MHz and 10 GHz. In square C1-15, it can be seen that this attenuation decreases as the frequency increases. In square C14-14 (or in any other square located inside of protective structure 10), it can be seen that, until a frequency on the order of one gigahertz is reached, the attenuation is much greater than for square C1-15. However, for frequencies on the order of from 1 to 2 GHz, the slope of curve C14-14 changes and the attenuation caused by isolating wall 15 becomes negligible. It can even be acknowledged that, for frequencies greater than 2 GHz, the isolating wall has a negative effect, that is, the attenuation of the signal from square C1-1 is smaller in square C14-14, which is “protected” by isolating structure 10 than in square C1-15, which is not protected.
Various theoretical explanations could be found for this phenomenon, which in any case is certainly due to the fact that the impedance of the connection of isolating wall 15 to ground becomes high. Thus, in prior art, various means for reducing the value of this impedance have been tried. One of these means is to use a so-called “flip-chip” semiconductor chip assembly mode in which the connection points on the chip are metallized and coated with conductive balls. Each conductive ball is then directly put in contact with a metallized region of a printed circuit board to which this chip is to be connected. Connections with a much smaller impedance than in the case where the chips are assembled in a package and connected to the package tabs by wires are thus obtained. However, this has not enabled completely solving the problem posed and has only partially improved the features of known protection structures.